DESIGN A COMPLETE HARDWARE ARCHITECTURE FOR MOTION DETECTION

Abstract

Nowadays, electronic devices have been applied every fields of life. The development of monitoring systems is also an evident. Monitoring system are widely used in many applications in transportation and security. So that, researching to develop and optimize the monitoring system is very important. The video received from the cameras has very huge amount so we get difficulty in transmitting and storing them. We need to reject the redundant information in order to reduce the amount of the video. There are several existing methods to solve this problem.

As the video received from fix station camera in certain applications has the same background so that we only need to transmit the motion objects. The video will be analyzed to detect the motion objects and then these objects will be compressed before being transmitted or stored. In this scheme, the motion detection process will determine the motion objects. There are several methods for motion detection such as statistical methods, optical flow, temporal differencing and background subtraction. After detection motion, the video will be compressed to reduce redundant information. Based on characteristic of image and the demand of the design, we can choose a suitable compression standard.

In this thesis, a complete hardware architecture for motion detection will be addressed. This architecture is composed of two main parts: motion detection and video compression. In motion detection, the ∑∆ estimation algorithm will be used. It is a simple and efficient algorithm based on background subtraction. In video compression, the JPEG standard will be used. JPEG is the most popular compression standard which is widely used in computer, digital cameras or smart phone. It has many advantages such as simple structure, high efficient, low cost.